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[Other resource] FIR_beh

Description: FIR滤波器的行为级VHDL源代码，可以任意修改滤波器级数，滤波器系数的精度为16比特。-FIR filter behavioral VHDL source code, which could be amended filter series. The filter coefficients for the 16-bit accuracy.
Platform: | Size: 1445 | Author: 郭兴波 | Hits:

[Other resource] filter-vhdl-code

Description: filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.
Platform: | Size: 173751 | Author: petri | Hits:

[VHDL-FPGA-Verilog] autofir

Description: 自适应滤波器设计的仿真程序，完全用C语言编写，可以作为滤波器设计的参考。原为VHDL实验要求的程序。-adaptive filter design simulation program, complete with C language can be used as filter design reference. VHDL to the original requirements of the experimental procedures.
Platform: | Size: 70656 | Author: 李博宁 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 里面是一个FIR滤波器的设计报告 里面有具体的 代码 等等 加法器 乘法器 见发起 等等 承平-There is a FIR filter design report there are specific code adder multiplier, etc., etc., see Cheng-Ping initiated
Platform: | Size: 189440 | Author: 丛宇 | Hits:

[VHDL-FPGA-Verilog] yl_cic32

Description: 一个三阶梳妆滤波器（CIC）的vhdl的源码-Dressing a third-order filter (CIC) of the VHDL source code
Platform: | Size: 1024 | Author: 白杨 | Hits:

[VHDL-FPGA-Verilog] FIR_verilog

Description: 基于verilog的FIR滤波器，有两种实现方法，分别给出仿真波形-Verilog based on the FIR filter, there are two methods, respectively, the simulation waveform
Platform: | Size: 628736 | Author: yejianchao | Hits:

[VHDL-FPGA-Verilog] fir_Verilog

Description: 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
Platform: | Size: 5120 | Author: yuming | Hits:

[VHDL-FPGA-Verilog] iir

Description: 数字信号处理的fpga实现，用VHDL语言编程实现IIR滤波器-Digital signal processing to achieve the FPGA, using VHDL language programming to achieve IIR filter
Platform: | Size: 1024 | Author: songjunmin | Hits:

[DSP program] fir_gen

Description: 数字信号处理的fpga实现，用VHDL语言编程实现FIR滤波器-Digital signal processing to achieve the FPGA, using VHDL language programming to achieve FIR filter
Platform: | Size: 1024 | Author: songjunmin | Hits:

[VHDL-FPGA-Verilog] halfband

Description: verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。-verilog halfband FIR
Platform: | Size: 1024 | Author: lv | Hits:

[Other] fir_16

Description: vhdl代码 实现16阶fir滤波器，可以仿真通过-vhdl code fir filter stage 16 can be adopted simulation
Platform: | Size: 3072 | Author: sumli | Hits:

[SCM] case4

Description: DA算法中的使用的查找表模块，本程序先设计查找表，然后设计4*4DA算法模块，之后进行位扩展和字扩展得到32阶滤波器程序.附带4各表，和FIR滤波器序数-DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extension of the procedure to be 32-order filter
Platform: | Size: 10240 | Author: 黄萌 | Hits:

[Other] IIR

Description: 毕业设计：基于FPGA的IIR滤波器设计-The design for IIR digital filter based on FPGA
Platform: | Size: 472064 | Author: lzndcb | Hits:

[VHDL-FPGA-Verilog] filtru_fi

Description: This is a filter fir implemeted in vhdl, i hope it will work :)
Platform: | Size: 1024 | Author: om | Hits:

[VHDL-FPGA-Verilog] 3

Description: FIR数字滤波器的优化与验证 -FIR digital filter optimization and verification FIR digital filter optimization and verification
Platform: | Size: 336896 | Author: 南才北往 | Hits:

[DSP program] fri

Description: 滤波器的设计的，用于FIR滤波器的设计和应用-The design of filters for the FIR filter design and application
Platform: | Size: 650240 | Author: qian | Hits:

[VHDL-FPGA-Verilog] fir_hdl

Description: 一个 FIR 滤波器的 verilog 实现， 与 matlab 产生的 reference code 相互验证。-Verilog a FIR filter to achieve, with the reference code generated by matlab mutual authentication.
Platform: | Size: 97280 | Author: wei | Hits:

[VHDL-FPGA-Verilog] LMS_filter

Description: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
Platform: | Size: 350208 | Author: rayax | Hits:

[VHDL-FPGA-Verilog] FIR

Description: The FIR digital filter algorithm is simulated and synthesized using VHDL
Platform: | Size: 2633728 | Author: Marija | Hits:

[VHDL-FPGA-Verilog] fir1

Description: this file consists of simple FIR filter designed with the fixed coefficients
Platform: | Size: 1024 | Author: bharat kumar | Hits:
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